Forum Discussion
tehjingy_Altera
Regular Contributor
2 years agoHi Ricardo
This you select the arm A53 under the Intel SoC FPGA during the target selection?
Intel SoC FPGA > Agilex > Bare Metal Debug > Debug Cortex-A53_0
Regards
Jingyang, Teh
- RicardoC2 years ago
Occasional Contributor
Hi Jingyang,
Thank you for the response. This is how it is configured:
It is a bit different that what you mentioned. Does it look OK?
Thank you,
Ricardo
- RicardoC2 years ago
Occasional Contributor
Do you have an update on how to configure the DK-DEV-AGI027RBES so that the HPS_JTAG signals of the Agilex part are in the JTAG chain?
Thank you,
Ricardo.