Duty-cycle of PLL's input clock

Hi

I attempted to generate a 20MHz 50% duty-cycle clock from a 20MHz 25% duty-cycle clock by the PLL of FPGA. However, the result is a 40MHz 50% duty-cycle clock.

The PLL parameters are :

(1) Input clock frequency : 20MHz

(2) M/N factor : 1/1

(3) Output duty-cycle : 50%.

The FPGA is EP2S180C3. The input 20MHz 25% duty-cycle clock is LVDS signal generated by another EP2S180C3 FPGA.

In addition :

Trial 1 : The 20MHz 50% duty-cycle clock could be generated when the PLL M/N factor is 1/2.

Trial 2 : The 20MHz 50% duty-cycle clock could be generated if change the duty cycle of input 20MHz clock to 50%, while the PLL M/N factor remains being 1/1.

Trial 3 : If change the duty cycle of input 20MHz clock to 10%, still 40MHz 50% duty-cycle clock is generated by the PLL.

I think the PFD (phase frequency detector) of PLL just detects the difference of rising edge between the reference clock and feedback clock, not related with duty-cycle, is that right?

Could anyone explain it?

Sincerely