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Altera_Forum
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14 years ago

Duty-cycle of PLL's input clock

Hi I attempted to generate a 20MHz 50% duty-cycle clock from a 20MHz 25% duty-cycle clock by the PLL of FPGA. However, the result is a 40MHz 50% duty-cycle clock. The PLL parameters are : ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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Just change the two FPGAs' clk pin I/O standard "LVDS" to "3.3-V LVTTL"

Could anyone explain it?

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I can hardly comment it without seeing the hardware and respective pin configuration related to termination and similar. I think, it's rather unlikely to get ringing edges in a correctly wired and terminated LVDS link.