Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorDuty-cycle of PLL's input clock
Hi I attempted to generate a 20MHz 50% duty-cycle clock from a 20MHz 25% duty-cycle clock by the PLL of FPGA. However, the result is a 40MHz 50% duty-cycle clock. The PLL parameters are : ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I think the PFD (phase frequency detector) of PLL just detects the difference of rising edge between the reference clock and feedback clock, not related with duty-cycle, is that right? --- Quote End --- Yes, presuming your measuremets are correct, most likely your input clock has ringing edges, causing double clocking.
