Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

dsp builder

hello everyone

I use dspbuilder design a project. I just want use it design a subsystem. But the signalcompile create a project(including the top level). How can I use dspbuilder create a VHDL files as a component to my project.

Thank you very much

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    in Signal Compiler, use the Export tab to create VHDL for your project

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    My name is Kenvin ! I like chilling out , chatting and having fun! I cant wait to make new friends! I hope everyone will treat me nice

    --- Quote End ---

    me too ! Thank you very much
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    in Signal Compiler, use the Export tab to create VHDL for your project

    --- Quote End ---

    Thank you very much! I had got it.

    but I have a new problem. I use dspbuilder create a FIR(N=64).But I compile it in quartusII with a error,the device just have 18 dsp block. How can I solve it? If I need design a high order FIR with fpga,how can I deal with it?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    you need to look at things like time division multiplexing/serializing the multiply and accumulate of the filter, or using constant coefficient multiplies in LEs

    DSP Builder Advanced Blockset or FIR Compiler II are really good at this sort of thing