DS-5 debugger "run" or "start" option lead HPS to reset

If you used the Qsys system that targeted the Arrow board and used it for your custom board did you remember to change the SDRAM to LPDDR2 and modify the timings? If not then that's probably what's wrong. After you generate the system you should also run the I/O constraints script for the SDRAM controller to make sure the necessary constraints are added for LPDDR2. For information about running the SDRAM constraints you can look at the Uniphy user manual which applies to the HPS memory controller as well.

I've tried to load unhosted preloader manually to both CPUs via debugger:

set semihosting enabled false
loadfile "C:\workspace\arm\Altera-SoCFPGA-HardwareLib-16550-CV-GNU\u-boot-spl"
run
stop

set semihosting enabled true
loadfile "C:\workspace\arm\Altera-SoCFPGA-HardwareLib-16550-CV-GNU\hwlib.axf"
start

I'll ping the software folks on my team to see if they have any ideas, unfortunately I haven't run much software on the SoC yet to know if something else needs to be done. You should hear back tomorrow, if not post here to send me a reminder.

If you try the following, does this work on your custom board?

set semihosting enabled false
loadfile "u-boot-spl.axf" 0x0
set semihosting enabled true
delete
tbreak spl_boot_device
run
wait
loadfile "hwlib.axf" 0x0
start

CLOCK: EOSC1 clock 25000 KHz
CLOCK: EOSC2 clock 25000 KHz
CLOCK: F2S_SDR_REF clock 0 KHz
CLOCK: F2S_PER_REF clock 0 KHz
CLOCK: MPU clock 925 MHz
CLOCK: DDR clock 400 MHz
CLOCK: UART clock 100000 KHz
CLOCK: MMC clock 50000 KHz
CLOCK: QSPI clock 370000 KHz
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION PASSED
SDRAM: 1024 MiB
SDRAM: ECC Enabled

U-Boot SPL 2013.01.01 (Jan 28 2015 - 17:56:44)
BOARD : Altera SOCFPGA Cyclone V Board
CLOCK: EOSC1 clock 25000 KHz
CLOCK: EOSC2 clock 25000 KHz
CLOCK: F2S_SDR_REF clock 0 KHz
CLOCK: F2S_PER_REF clock 0 KHz
CLOCK: MPU clock 800 MHz
CLOCK: DDR clock 300 MHz
CLOCK: UART clock 100000 KHz
CLOCK: MMC clock 3125 KHz
CLOCK: QSPI clock 3125 KHz
RESET: COLD
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION PASSED
SDRAM: 512 MiB
SDRAM: Scrubbing 0x01000000 - 0x02000000
SDRAM: Scrubbing success with 27 ms
SDRAM: Scrubbing 0x00000000 - 0x01000000
SDRAM: Scrubbing 0x02000000 - 0x20000000

+reset system
+stop
WARNING(CMD315): Target is not running
+set semihosting enabled false
+loadfile "C:\workspace\arm\Altera-SoCFPGA-HardwareLib-16550-CV-GNU\u-boot-spl"
Target has been reset
Loaded section .text: S:0xFFFF0000 ~ S:0xFFFF67A3 (size 0x67A4)
Loaded section .rodata: S:0xFFFF67A4 ~ S:0xFFFF87E6 (size 0x2043)
Loaded section .data: S:0xFFFF87E8 ~ S:0xFFFF94EF (size 0xD08)
Entry point S:0xFFFF0000
Execution stopped at: S:0xFFFF0004
S:0xFFFF0004   40,0   ldr   pc, _undefined_instruction
+delete
All user breakpoints deleted
+tbreak spl_boot_device
Breakpoint 1 at S:0xFFFF14AC
    on file spl.c, line 71
    on file spl.c, line 81
+run
Reloading program
Starting target with image C:\workspace\arm\Altera-SoCFPGA-HardwareLib-16550-CV-GNU\u-boot-spl
Running from entry point
+wait
Execution stopped at breakpoint 1: S:0xFFFF14AC
In spl.c
S:0xFFFF14AC   71,0   {
Deleted temporary breakpoint: 1
+loadfile "C:\workspace\arm\Altera-SoCFPGA-HardwareLib-16550-CV-GNU\hwlib.axf"
Loaded section .ARM.exidx: S:0x00126694 ~ S:0x0012669B (size 0x8)
Loaded section .text: S:0x00100000 ~ S:0x0012661F (size 0x26620)
Loaded section .eh_frame: S:0x00126620 ~ S:0x00126693 (size 0x74)
Loaded section .ARM.exidx: S:0x00126694 ~ S:0x0012669B (size 0x8)
Loaded section .rodata: S:0x001266A0 ~ S:0x0012720F (size 0xB70)
Loaded section .data: S:0x00127210 ~ S:0x00127BC7 (size 0x9B8)
Entry point S:0x00100040
+set semihosting enabled true
Semihosting server socket created at port 8000
WARNING(TAB139): Semihosting was enabled after the target had started running so may not work correctly. Enable semihosting in a target initialization debugger script or with an image symbol instead
+start
Starting target with image C:\workspace\arm\Altera-SoCFPGA-HardwareLib-16550-CV-GNU\hwlib.axf
Running from entry point
interrupt
Execution stopped at: S:0xFFFF0004
S:0xFFFF0004   LDR      pc, ;  = 0xFFFF0020

WARNING(TAB139): Semihosting was enabled after the target had started running so may not work correctly. Enable semihosting in a target initialization debugger script or with an image 

Well, at least the warning is gone. :)

It seems to me I've fixed this issue :)

MEMORY
{
  boot_rom (rx) : ORIGIN = 0xfffd0000, LENGTH = 64K
  oc_ram (rwx) : ORIGIN = 0xffff0000, LENGTH = 64K
  /* Need to have 64bytes available before start of program, to store the mkimage header */
  ram (rwx) : ORIGIN = 0x100000 + 0x40, LENGTH = 511M - 0x40
}