Forum Discussion
Altera_Forum
Honored Contributor
11 years agoIf you try the following, does this work on your custom board?
set semihosting enabled false
loadfile "u-boot-spl.axf" 0x0
set semihosting enabled true
delete
tbreak spl_boot_device
run
wait
loadfile "hwlib.axf" 0x0
start This will wait for uboot to reach a safe location in the code. The 0xffff0020 location is the undefined instruction vector, so it could be possible that the LPDDR2 memory is corrupted or has some timing issue. Can you copy the output from u-boot as well? Does it report that calibration has passed (see below as an example) on your board? CLOCK: EOSC1 clock 25000 KHz
CLOCK: EOSC2 clock 25000 KHz
CLOCK: F2S_SDR_REF clock 0 KHz
CLOCK: F2S_PER_REF clock 0 KHz
CLOCK: MPU clock 925 MHz
CLOCK: DDR clock 400 MHz
CLOCK: UART clock 100000 KHz
CLOCK: MMC clock 50000 KHz
CLOCK: QSPI clock 370000 KHz
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION PASSED
SDRAM: 1024 MiB
SDRAM: ECC Enabled