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#  ** Error: (vsim-3010)  - Module 'sopc_system_tb' does not have a `timescale directive in effect, but other modules do.#  Region: /sopc_system_tb/dut/the_master_bfm/master_bfm

`timescale 1ns / 1ps

do setup_sim.do
s
vlog -sv sopc_system_tb.sv
vsim -t ps -novopt +nowarnTFMPC sopc_system_tb
do sopc_system_tb.do
run -a 

I am using ModelSim Altera Starter Edition vsim 6.6c Simulator 2010.08 Aug 24 2010.

#  ** Error: (vsim-3010)  - Module 'sopc_system_tb' does not have a `timescale directive in effect, but other modules do.#  Region: /sopc_system_tb/dut/the_master_bfm/master_bfm

Thanks for the example. I will try to learn as much as I can from this. But at step (d) when I type s, I get the following error message:

#  ** Error: (vsim-3010)  - Module 'sopc_system_tb' does not have a `timescale directive in effect, but other modules do.#  Region: /sopc_system_tb/dut/the_master_bfm/master_bfm

Here's a verification example. The SOPC System contains an Avalon-MM BFM master, an on-chip RAM, and a PIO component. The readme.txt file explains how to rebuild the system.

 
// console messaging level
`define VERBOSITY VERBOSITY_INFO
 
//BFM related parameters
`define ST_SYMBOL_W      8
`define ST_NUMSYMBOLS    1
`define ST_CHANNEL_W     1
`define ST_ERROR_W       1
`define ST_READY_LATENCY 0
//local parameters
`define ST_DATA_W `ST_SYMBOL_W * `ST_NUMSYMBOLS
 
module learn_verification_ip_test();
  import verbosity_pkg::*;
 
  endmodule
 

// Simulation tool : ModelSim-Altera (Verilog)
// 
 
`timescale 1 ps/ 1 ps
module main_edge_detection_streaming_vlg_tst();
// constants                                           
// general purpose registers
reg eachvec;
// test vector input registers
reg clk;
reg  in_data;
reg in_empty;
reg in_endofpacket;
reg in_startofpacket;
reg in_valid;
reg out_ready;
reg reset;
// wires                                               
wire in_ready;
wire   out_data;
wire out_empty;
wire out_endofpacket;
wire   out_hw_counter;
wire out_startofpacket;
wire out_valid;
// assign statements (if any)                          
main_edge_detection_streaming i1 (
// port map - connection between master ports and signals/registers   
 .clk(clk),
 .in_data(in_data),
 .in_empty(in_empty),
 .in_endofpacket(in_endofpacket),
 .in_ready(in_ready),
 .in_startofpacket(in_startofpacket),
 .in_valid(in_valid),
 .out_data(out_data),
 .out_empty(out_empty),
 .out_endofpacket(out_endofpacket),
 .out_hw_counter(out_hw_counter),
 .out_ready(out_ready),
 .out_startofpacket(out_startofpacket),
 .out_valid(out_valid),
 .reset(reset)
);
 
 reg   storage_values ; //153600 values for 640x240 image
 integer fileId, fileOutput;
 
initial                                                
begin                                                  
// code that executes only once   
  clk = 1'b1; 
 
// Do the hexadecimal reads from the txt file
$readmemh("hexval_test_1d.txt", storage_values);
 
// ouput result will be sent to a text file
fileOutput = $fopen("result_sobel.txt", "w"); 
 
reset = 1'b0;
in_empty = 1'b1;
in_startofpacket = 1'b1;
in_valid = 1'b1;
in_endofpacket = 1'b0; 
//in_ready = 1'b1;
 
//Stop after 1536000 clock cycles ??# 1536000 in_endofpacket = 1'b1; 
 
$display("Running testbench");                       
end      
 
// Control the clock signal
 initial
  begin
    forever# 5 clk = ~clk;
  end
 
integer i; 
initial    
begin                                                  
   for (i=0; i < 153600; i=i+1)
 begin
  @(posedge clk);
  in_data = storage_values;
    $fwrite(fileOutput,"%d\n",out_data); 
 end
@eachvec;                                              
 
end                                                    
endmodule
 

Thanks for the files Dave. Have you just dowloaded them from somewhere or do you just happen to have these files on your computer?

if possible, please feed this back to Altera. i have had similar problems