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Have you just dowloaded them from somewhere or do you just happen to have these files on your computer?
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I had copies on my computer.
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To get to the verification tool itself, I was able to run the tutorial files. Now I want to do the same thing on my own component which has Avalon ST interface. I followed all the steps ...
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Ignoring the VIP manual, here's what I do. I create an SOPC System with the Avalon BFM components, and then I let Quartus generate the simulation scripts for me (check the checkbox in SOPC Builder before clicking generate), eg., for a system called sopc_builder, a folder called sopc_builder_sim will be created in your project folder. Within that folder is a setup_sim.do script. Use this as a template for a new Tcl script to build the sopc_system files. Throw everything else away.
Within the generated sopc_system.v file, there is a testbench. Ignore it, its useless (well, mostly useless, see the comment below).
Create your own SystemVerilog testbench and instantiate a copy of the sopc_system. Use the hierarchical path to the BFMs to call their Verification IP API functions.
I've only been working with Avalon-MM BFM masters, but this technique should work with Avalon-ST BFM masters too.
The key thing to understand is that the Verification Suite cannot read your mind, so the automatic testbench it provides is pretty simple, but only because it has to be. Just think of it as a tool compilation test, i.e., you can build the design with Modelsim and vsim it, but it does not do anything interesting, eg., like actually test your design :)
Cheers,
Dave
Honored Contributor
