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I am using ModelSim Altera Starter Edition vsim 6.6c Simulator 2010.08 Aug 24 2010.
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I'll try it with a Modelsim-ASE version and see what I get.
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Assuming we get this error cleared, do you think I can still achieve what I'm trying to do, i.e. read values from text file, simulate component, and save output to another text?
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Yep, absolutely. SystemVerilog is both a programming language and a hardware language. Whatever you can do in C/C++, there is something similar in SystemVerilog. You can even link C to SystemVerilog ... but I'm not sure if Modelsim-ASE supports that.
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In your sopc_system_tb.sv file, I can see that I will have to modify the two tasks avalon_write_single and avalon_read_single to be able to do what I want, but I don't know how to do that yet and it does seem a bit complicated for a relatively simple thing to do if I was testing a code in C for example.
I was just wondering whether this is the best way for me to test a hardware module. Or perhaps everything is complicated with FPGAs... damn I should have stuck with C coding :)
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I suspect you were just doing simple C code.
The real world is much more complicated. Testing code at the component level, and then at the system-level takes extra effort. But that effort pays off big-time when you do not have to debug difficult problems; you avoided them by putting in the extra work up-front.
For example, when you write C code, do you write 'unit tests' to ensure that every C function does what it is supposed to do given correct inputs and incorrect inputs? Do you have a 'make check' build command that confirms every test passes. Do you have a continuous-integration build system, where your system-level code is checked out of a code repository and is continually built and checked ... The complexity of real-world development occurs everywhere :)
Cheers,
Dave
Honored Contributor
