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I create an SOPC System with the Avalon BFM components, and then I let Quartus generate the simulation scripts for me (check the checkbox in SOPC Builder before clicking generate), eg., for a system called sopc_builder, a folder called sopc_builder_sim will be created in your project folder. Within that folder is a setup_sim.do script. Use this as a template for a new Tcl script to build the sopc_system files. Throw everything else away.
Within the generated sopc_system.v file, there is a testbench. Ignore it, its useless (well, mostly useless, see the comment below).
Create your own SystemVerilog testbench and instantiate a copy of the sopc_system. Use the hierarchical path to the BFMs to call their Verification IP API functions.
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Thanks for the suggestions Dave. I've followed the initial steps but got lost at the stage of creating my own SystemVerilog testbench because I don't how how to write it. I looked at SystemVerilog tuts and I could only write the lines below. Could anybody give a few pointers on how to do the full testbench code?
// console messaging level
`define VERBOSITY VERBOSITY_INFO
//BFM related parameters
`define ST_SYMBOL_W 8
`define ST_NUMSYMBOLS 1
`define ST_CHANNEL_W 1
`define ST_ERROR_W 1
`define ST_READY_LATENCY 0
//local parameters
`define ST_DATA_W `ST_SYMBOL_W * `ST_NUMSYMBOLS
module learn_verification_ip_test();
import verbosity_pkg::*;
endmodule
The module I want to test is a University Program IP module called Video Edge Detection (see attachment) which takes in 8-bit values and outputs 8-bit values as well. But the module takes in a series of data values to represent a frame of data values. I found out that $readmemh is useful in my case. I want to be able to read the data values from a text file using $readmemh, and write the results also back to another text file. Will I be able to do that in SystemVerilog and BFM?
As I couldn't get anywhere with the BFM components, I tried creating a testbench for that component as below without using BFM or SystemVerilog. But here again, I don't think it is good as I am not getting any meaningful results when I try to run it in ModelSim. Any suggestion is greatly appreciated.
// Simulation tool : ModelSim-Altera (Verilog)
//
`timescale 1 ps/ 1 ps
module main_edge_detection_streaming_vlg_tst();
// constants
// general purpose registers
reg eachvec;
// test vector input registers
reg clk;
reg in_data;
reg in_empty;
reg in_endofpacket;
reg in_startofpacket;
reg in_valid;
reg out_ready;
reg reset;
// wires
wire in_ready;
wire out_data;
wire out_empty;
wire out_endofpacket;
wire out_hw_counter;
wire out_startofpacket;
wire out_valid;
// assign statements (if any)
main_edge_detection_streaming i1 (
// port map - connection between master ports and signals/registers
.clk(clk),
.in_data(in_data),
.in_empty(in_empty),
.in_endofpacket(in_endofpacket),
.in_ready(in_ready),
.in_startofpacket(in_startofpacket),
.in_valid(in_valid),
.out_data(out_data),
.out_empty(out_empty),
.out_endofpacket(out_endofpacket),
.out_hw_counter(out_hw_counter),
.out_ready(out_ready),
.out_startofpacket(out_startofpacket),
.out_valid(out_valid),
.reset(reset)
);
reg storage_values ; //153600 values for 640x240 image
integer fileId, fileOutput;
initial
begin
// code that executes only once
clk = 1'b1;
// Do the hexadecimal reads from the txt file
$readmemh("hexval_test_1d.txt", storage_values);
// ouput result will be sent to a text file
fileOutput = $fopen("result_sobel.txt", "w");
reset = 1'b0;
in_empty = 1'b1;
in_startofpacket = 1'b1;
in_valid = 1'b1;
in_endofpacket = 1'b0;
//in_ready = 1'b1;
//Stop after 1536000 clock cycles ??# 1536000 in_endofpacket = 1'b1;
$display("Running testbench");
end
// Control the clock signal
initial
begin
forever# 5 clk = ~clk;
end
integer i;
initial
begin
for (i=0; i < 153600; i=i+1)
begin
@(posedge clk);
in_data = storage_values;
$fwrite(fileOutput,"%d\n",out_data);
end
@eachvec;
end
endmodule
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