Good night everybody , I have problem of QuartusII 10.1sp1 . My user chip is CycloneII EP2C35FC8 , when my sopc builder use Pll&#12289;SDRAM&#12289;FLASH&#12289;MCU&#12289;JTAG , I can run as hardware of holld_world . (Eclipse - Application and BSP from Template) But , when I return sopc builder and add EnthModule&#12289;DMA(*2-RX&#12289;TX)&#12289; onchip momery(4096bytes)&#12289;timer . And Auto-Assign Base Addres&#12289;IRQS. Compilation after , I run as web_server_socket(rgmii) (Eclipse - Application and BSP from Template) , but message tell me , downloading elf process failed . So , I try again run as holld_world , but message still tell me downloading elf process failed . Would like to ask anyone encountered a similar problem : ( ?

You should have another error message before this one that tells you why the download failed. Do you have a system id component in your sopc project? If not then add it first. It will ensure that you are using the correct configuration. IF you don't have a license for the Nios CPU you are using, then there is an opencore evaluation window that will open after you configure the FPGA. Don't close this window or the CPU will stop working. Check also that the design is properly constrained and meet all timing requirements.

Dear Daixiwen Thanks your answer , I found my sopc builder , haven't System id component , so I add this component , moreover move the top and Auto-Assign Base Addres&#12289;IRQS . when I finish compilation , I programmer project for my board . (still keep open the programmer window) Then I use Eclipse and creat Application and BSP from Template . When I run as web_server_socket(rgmii) , the message still tell me downloading elf process failed but appear the message befor , have other message . The message tell me assertion "m_state==state_debug" failed : file "nios2oci.cpp",line 158 using cable "usb-blaster [usb-0]", device 1 , instance 0x00 pausing target processor : not responding . resetting and trying again : /cygdrive/c/altera/10.1sp1 /nios2eds/bin/nios2-download : line 601: 2380 hangup.

--- Quote Start --- pausing target processor : not responding . --- Quote End --- This usually means one of the following:[list][*]you are in opencore evaluation mode and you closed the window after programming the FPGA[*]bad clock and/or reset signals[*]design not meeting timing requirements[/list]

Dear Daixiwen I reference your support and read some datasheet . I found , my problem maybe come from my memory config . In my project , when I just use (sopc builder) pll&#12289;nios&#12289;sdram&#12289;flash&#12289;jtag haven't problem . But , when I add Enth Module&#12289;DMA&#12289;on-chip(ram or rom) the niosII will tell me downloading elf process failed of project Near, I read datasheet of page 6 http://www.altera.com/literature/manual/mnl_avalon_spec.pdf I think ,maybe I need use FIFO Buffer(on-chip) replace on-chip(ram or rom) but I still tree , because i first use this fifo buffer(on-chip)

Is your design properly constrain and does it meet all timing requirements? When a design stop workings after adding some components usually indicates a timing problem. Adding some components should not cause the processor not to respond on the JTAG interface.

Altera_Forum

Honored Contributor

14 years ago

Downloading ELF Process failed of Project

Good night everybody , I have problem of QuartusII 10.1sp1 .

My user chip is CycloneII EP2C35FC8 , when my sopc builder use

Pll、SDRAM、FLASH、MCU、JTAG , I can run as hardware of holld_world .

(Eclipse - Application and BSP from Template)

But , when I return sopc builder and add EnthModule、DMA(*2-RX、TX)、

onchip momery(4096bytes)、timer . And Auto-Assign Base Addres、IRQS.

Compilation after , I run as web_server_socket(rgmii)

(Eclipse - Application and BSP from Template) ,

but message tell me , downloading elf process failed .

So , I try again run as holld_world , but message still tell me

downloading elf process failed .

Would like to ask anyone encountered a similar problem : ( ?

27 Replies

Altera_Forum
Honored Contributor
14 years ago
Dear Daixiwen

My project of software at the \Myweb_server_bsp\drivers\src

indeed have altera_avalon_tse.c , and inside file , indeed have

support about 88E1111 message .

But I still not understand , my led indicate denormal of reason .

(LED_LINK1000 Right , LED_LIN100 Unright...)

And about MDIO communication problem, I not understand your mean..
Altera_Forum
Honored Contributor
14 years ago
Dear Daixiwen

LED indicate is solve (normal : LED_RX、LED_DUPLEX、LED_LINK100)

Because the problem from my pin planner of voltage config .

(need set to 2.5V Level)

But NiosII message still tell me

error : mac group[0] - no phy connected!
error : phy[0.0] - no phy connected!speed=100,duplex=full

MDIO communication ... I will try : )
Altera_Forum
Honored Contributor
14 years ago
Dear Daixiwen

I can catch PHY!! indeed is hardware of MDIO problem .

Now NiosII message tell me

Your Enthenet MAC address is 00:07:ed:ff:3d:e5
prepped 1 interface , initalzing...
[tse_mac_init]
INFO : TSE MAC 0 found at address 0x05002000
INFO : PHY Marvell 88E1111 found at PHY address 0x10 of MAC Group[0]
INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0]
INFO : PHY[0.0] - Restart Auto-Negotiation , checking PHY link...
INFO : PHY[0.0] - Auto-Negotiation PASSED.
MARVELL : Mode changed to RGMII/Modified MII to Copper mode
MARVELL : Enable RGMII Timing Control
MARVELL : PHY reset
INFO : PHY[0.0] - Checking link...
INFO : PHY[0.0] - Link not yet established , restart auto-negotiation...
INFO : PHY[0.0] - Auto-Negotiation PASSED
INFO : PHY[0.0] - Link established
INFO : PHY[0.0] - Speed = 100 , Duplex = Full
OK , x=0 , CMD_CONFIG=0x00000000

MAC post-initalization : CMD_CONFIG=0x04000203
[tse_sgdma_read_init] RX descriptor chain desc (1 depth) created
mctest init called
IP address of et1 : 0.0.0.0

But...now I still not Catch IP ... and LED message indicate is not denormal.

(LED_TX unright)

I try of de2-115 board test web_server_socket , and function is normal.

(LED_TX right) so ... I exclude Internet cable problem of possibility ... I

think maybe is my TX_DATA Problem...
Altera_Forum
Honored Contributor
14 years ago
This line
--- Quote Start ---
IP address of et1 : 0.0.0.0
--- Quote End ---
shows that your board isn't getting an IP. Try to set a static IP address in the code yourself or use a DHCP server.
Altera_Forum
Honored Contributor
14 years ago
Dear Daixiwen

I setting static IP address of file simple_socket_server.h

but TX_LED just bright look and unright...and I try use super terminal ,

but still not connect ... (I have set SSS_PORT)
Altera_Forum
Honored Contributor
14 years ago
Do you see the correct address in the nios console? If not it means the Interniche Stack isn't picking up the IP address you set.
You should try and use a sniffer such as Wireshark to see if the board is answering any ARP requests.
Altera_Forum
Honored Contributor
14 years ago
I have solved the problem by locking the address of all the components in the NIOS II processer! This problem confused me several days. At last, I remove it!

Forum Discussion

Downloading ELF Process failed of Project

27 Replies

Recent Discussions

Agilex 5 FPGA EMIF: sharing LPDDR4 reference clock between Bank 3A and Bank 3B

Functional fail and suspect relate to the component

Cyclone IV GX Invalid JTAG ID Code - EPCS32

Agilex 7 - Incorrect Device ID in Programmer

MT25Q512 Programming Issue When Connected to Cyclone 10CX150Y