Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Downloading ELF Process failed of Project

Good night everybody , I have problem of QuartusII 10.1sp1 .

My user chip is CycloneII EP2C35FC8 , when my sopc builder use

Pll、SDRAM、FLASH、MCU、JTAG , I can run as hardware of holld_world .

(Eclipse - Application and BSP from Template)

But , when I return sopc builder and add EnthModule、DMA(*2-RX、TX)、

onchip momery(4096bytes)、timer . And Auto-Assign Base Addres、IRQS.

Compilation after , I run as web_server_socket(rgmii)

(Eclipse - Application and BSP from Template) ,

but message tell me , downloading elf process failed .

So , I try again run as holld_world , but message still tell me

downloading elf process failed .

Would like to ask anyone encountered a similar problem : ( ?

27 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    You should have another error message before this one that tells you why the download failed.

    Do you have a system id component in your sopc project? If not then add it first. It will ensure that you are using the correct configuration. IF you don't have a license for the Nios CPU you are using, then there is an opencore evaluation window that will open after you configure the FPGA. Don't close this window or the CPU will stop working.

    Check also that the design is properly constrained and meet all timing requirements.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Dear Daixiwen

    Thanks your answer , I found my sopc builder ,

    haven't System id component , so I add this component ,

    moreover move the top and Auto-Assign Base Addres、IRQS .

    when I finish compilation , I programmer project for my board .

    (still keep open the programmer window)

    Then I use Eclipse and creat Application and BSP from Template .

    When I run as web_server_socket(rgmii) , the message still tell me

    downloading elf process failed

    but appear the message befor , have other message .

    The message tell me

    assertion "m_state==state_debug" failed : file

    "nios2oci.cpp",line 158

    using cable "usb-blaster [usb-0]", device 1 , instance 0x00

    pausing target processor : not responding .

    resetting and trying again : /cygdrive/c/altera/10.1sp1

    /nios2eds/bin/nios2-download : line 601: 2380 hangup.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    pausing target processor : not responding .

    --- Quote End ---

    This usually means one of the following:[list][*]you are in opencore evaluation mode and you closed the window after programming the FPGA[*]bad clock and/or reset signals[*]design not meeting timing requirements[/list]
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Dear Daixiwen

    I reference your support and read some datasheet .

    I found , my problem maybe come from my memory config .

    In my project , when I just use (sopc builder)

    pll、nios、sdram、flash、jtag haven't problem .

    But , when I add Enth Module、DMA、on-chip(ram or rom)

    the niosII will tell me downloading elf process failed of project

    Near, I read datasheet of page 6

    http://www.altera.com/literature/manual/mnl_avalon_spec.pdf

    I think ,maybe I need use FIFO Buffer(on-chip) replace on-chip(ram or rom)

    but I still tree , because i first use this fifo buffer(on-chip)
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Is your design properly constrain and does it meet all timing requirements? When a design stop workings after adding some components usually indicates a timing problem. Adding some components should not cause the processor not to respond on the JTAG interface.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Dear Daixiwen

    sorry Daixiwen , I don't know your mean ...

    My timing requirements problem of your mean ?

    but my pll only fore clk clk_0(exteral 50MHZ) 、system_clk(100MHZ) 、

    sdram_clk(100MHZ -65deg) 、 enth_clk(25MHZ).

    At my sopc builder , only pll use clk_0 , other every use system_clk.

    To Blcok Diagram/Schematic File , sdram_clk for sdram clk of pin

    Enth_clk for Enth clk of pin , I still don't know my problem from where...
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    You must create an sdc file that lists at least all your external clocks. Then when you compile your design, look for any critical warning saying the timing requirements haven't been met. Have also a look in Timequest for the clock report and check that all your clocks have been detected correctly and are at the right frequency.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Yes you have to define in .sdc files your clocks and timing to all fast I/O pins (memories and Ethernet). If you use a development kit you probably have some example designs with ready made .sdc files.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Dear Daixiwen

    So , I need read data(CyclonII、Sdram、Flash、Enth Chip...)

    and set Timing parameter of your mean ?

    And new question , I thinking maybe my problem ,

    come from my on-chip(Enth use) timing set ... because

    when I remove on-chip , my NiosII haven't problme.

    but , when I add Enth Module 、 DMA 、on-chip ...

    and my friend tell me , maybe my problem come from the on-chip Timing.

    But at Sopc builder , I not found about set Timing parameter of on-chip...