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ElShang's avatar
ElShang
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7 months ago
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Does altering the FPGA IO standard actually change something in hardware?

Hello to the community. Here is a background/precondition of the question in the heading. I entered the realm of FPGA development using Verilog, DE10-Lite (MAX10 series) and Quartus Prime Lite Editi...
Generic Io
Programmable Logic Device
  • Farabi_Altera's avatar
    Farabi_Altera
    6 months ago

    Hello, 

     

    VCCIO if powering the IO banks of the IO , depending of where the IO is located. 

    eg. If you power VCCIO -> 3.3V, the IO standard located in that IO bank should be 3.3V based IO. 
    The IO assignment in Quartus pin planner must be aligned with the physical setup on your board. 

     

    regards,

    Farabi 

FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
7 months ago

Hi,

I believe I already explained here that the problem isn't related to IO-Standards rather than inappropriate clock source. 

(134) Does altering the FPGA IO standard actually change something in hardware? | Forum for Electronics

You are specifically asking if changing the IO-Standard affects input signal processing. Short answer is, as long as you don't activate Schmitt Trigger or use a completely different IO type (e.g. voltage referenced or differential), it does not. Input threshold is a partly affected by actual bank voltage but less than proportianal for MAX10 series according to datasheet.

An IOE description beyond the details given in Device Manual isn't publically available, I fear.

Regards Frank

ElShang's avatar
ElShang
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7 months ago

Kindly thanks for your reply.

It never hurts to ask a question at multiple resources. :-)

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    7 months ago

    Right, this is the best place to ask Altera FPGA related questions.