Contributor
Contributor@RichardTanSY_Altera, thanks for the reply.
I'm already well acquainted with this document. I've been attempting to use the IOPLL IP, and finding that it's not working as expected per this document.
This document fails to explain what I'm seeing, and thus far so does this community forum (see: https://community.intel.com/t5/Programmable-Devices/Clock-synthesis-and-de-skewing-using-an-IOPLL-in-Arria-10/m-p/1294531 )
So there's the catch 22. The generated IP doesn't seem to be working right, and at the same time it obscures what's really going on underneath, which is making it impossible to debug. Hence the desire to gain better visibility into what's really happening at the WYSIWYG level.
If Altera can't/won't provide visibility at the WYSIWYG level, what else do you suggest?
Thanks,
-Roee
Super ContributorYou can view the twentynm_iopll components in the twentynm_components.vhd file at the <installation libraries>\quartus\libraries\vhdl\wysiwyg
I am not sure if this will helps you in anyway as there is no documentation on this.
If an IP is not working as expected as what written in the documentation, this may be potentially a bug.
If so, you can send us a simple design that duplicate the error and we will get the engineering to check on this.
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.
