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NBK's avatar
NBK
Icon for New Contributor rankNew Contributor
2 years ago

Digital input slew rate or rise time, fall time requirements for 10M16SCU169I7G

Hello, Does 10M16SCU169I7G FPGA has any constraints for DIgital input slew rate or maximum allowed rise/fall times. if yes, what are the maximum allowed limits? Thanking you in advance.
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FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
2 years ago
I don't see explicite specification in datasheet. If you have input signals with slow edges, consider to enable schmitt-trigger feature for respective inputs.