Digital clock using verilog HDL

Hi Eraesh,

Personally I will encourage you to try and face it yourself as it is in your interest but I can suggest these guide lines.

First forget about HDL coding but focus on how to do your design. You will need a suitable reference clock. run a counter on this clock and generate pulses for seconds/min/hrs then counters for seconds/minutes/hours that overflow as appropriate e.g. "seconds" counter running from 0 to 59 ...etc.

design an algorithm for stop watch and a detection algorithm for alarm based n above three counters.

once you get your counting ready, you need to display them. One way is to convert them from binary to BCD then decode that for the 7 segment display.

Of course you need to consider refresh rate for display and define your inputs, these may include reset,ref clk,user inputs for time-setting or alarm-settings or stop-watch...your outputs will be the decoded values for say 8 display digits such as 00:00:00 as well as the alarm beep...

Hope this helps

Regards

Kaz

oh, i'm sorry. my problem is i don't know how to separate digital display 1-4 from each other. i can make counter counting from 0000 to 9999 but i don't know how to make it 00:59. also, if it reaches 00:59, how can i make it 01:00.?

we have to display hh:mm and mm:ss when we use the dip switches.

thank you for responding. :)

i have here the codes. but when i program the fpga, it displays 8888 only. it doesn't count. it was stationary.

module clock (clk, rst, m1, m2, m3, m4, a, b, c, d, e, f, g, dp);

input clk, rst;

output m1, m2, m3, m4;

output a, b, c, d, e, f, g, dp;

reg[23:0] timer;

reg[19:0] state;

reg[7:0] number, disp1, disp2, disp3, disp4;

reg c1, c2, c3, c4, digit1, digit2, digit3, digit4;

assign m1=digit1;

assign m2=digit2;

assign m3=digit3;

assign m4=digit4;

assign{a, b, c, d, e, f, g}=number;

assign dp=1;

parameter number1=7'b1001111;

parameter number2=7'b0010010;

parameter number3=7'b0000110;

parameter number4=7'b1001100;

parameter number5=7'b0100100;

parameter number6=7'b0100000;

parameter number7=7'b0001111;

parameter number8=7'b0000000;

parameter number9=7'b0000100;

parameter number0=7'b0000001;

always @(posedge clk)

if (rst==0)

state<=4'b0000;

else

state<=4'b1111;

always @ (posedge clk)

if (rst==0)

timer <=0;

else if (timer ==16000000)

timer <=0;

else

timer <= timer+1;

always @ (posedge clk)

if (rst==0)

begin

digit1<=0;

c1<=0;

end

else if (digit1==9&&timer==16000000)

begin

digit1<=0;

c1<=1;

end

else

begin

digit1<=digit1+1;

end

always @ (posedge clk)

if (rst==0)

begin

digit2<=0;

c2<=0;

end

else if (digit2==9&&c1)

begin

digit2<=0;

c2<=1;

end

else

begin

digit2<=digit2+1;

end

always @ (posedge clk)

if (rst==0)

begin

digit3<=0;

c3<=0;

end

else if (digit3==9&&c2)

begin

digit3<=0;

c3<=1;

end

else

begin

digit3<=digit3+1;

end

always @ (posedge clk)

if (rst==0)

begin

digit4<=0;

c4<=0;

end

else

begin

digit4<=digit4+1;

end

always @(posedge clk)

case (digit1)

4'b0000:disp1<=number0;

4'b0001:disp1<=number1;

4'b0010:disp1<=number2;

4'b0011:disp1<=number3;

4'b0100:disp1<=number4;

4'b0101:disp1<=number5;

4'b0110:disp1<=number6;

4'b0111:disp1<=number7;

4'b1000:disp1<=number8;

4'b1001:disp1<=number9;

default:disp1<= number0;

endcase

always @(posedge clk)

case (digit2)

4'b0000:disp2<=number0;

4'b0001:disp2<=number1;

4'b0010:disp2<=number2;

4'b0011:disp2<=number3;

4'b0100:disp2<=number4;

4'b0101:disp2<=number5;

4'b0110:disp2<=number6;

4'b0111:disp2<=number7;

4'b1000:disp2<=number8;

4'b1001:disp2<=number9;

default:disp2<= number0;

endcase

always @(posedge clk)

case (digit3)

4'b0000:disp3<=number0;

4'b0001:disp3<=number1;

4'b0010:disp3<=number2;

4'b0011:disp3<=number3;

4'b0100:disp3<=number4;

4'b0101:disp3<=number5;

4'b0110:disp3<=number6;

4'b0111:disp3<=number7;

4'b1000:disp3<=number8;

4'b1001:disp3<=number9;

default:disp3<= number0;

endcase

always @(posedge clk)

case (digit4)

4'b0000:disp4<=number0;

4'b0001:disp4<=number1;

4'b0010:disp4<=number2;

4'b0011:disp4<=number3;

4'b0100:disp4<=number4;

4'b0101:disp4<=number5;

4'b0110:disp4<=number6;

4'b0111:disp4<=number7;

4'b1000:disp4<=number8;

4'b1001:disp4<=number9;

default:disp4<= number0;

endcase

endmodule

**my problem is the increasing of the value of the second digit, and the third and the fourth. what is wrong with my codes.? do i need to use an identifier or any other special codes.? because the ones i used were the only thing i knew. as i have said, i only know basic stuffs. i know i should learn more. please help me. thanks. :)

I'm not a verilog specialist, but for starters, I think there is a problem with your first digit.

If I understand correctly, you want to increase the digit by one each time your timer value resets (i.e. every 16000000 clock cycles). But you only do this test when the digit is 9. Furthermore you never put back the c1 signal at '0' so your other digits will increase on each clock cycle after that. You should do it this way:

[list][*]first test if reset is enabled, and in that case put the digit at 0

[*]else test if the timer is equal to your maximum value (or any fixed value in fact, you could use 0) and only then, do the following:[list][*]if the digit is 9, put it at 0 and assert the c1 signal[*]in the other cases, increase it by 1 and de-assert the c1 signal[/list][*]if the timer isn't equal to your fixed value, de-assert the c1 signal[/list]

Your digit1,digit2,digit3,digit4 are single bit registers they can store 0 or 1 but you are trying to increment it from binary values 0 to 9.

use reg [3:0] digit1 and so on to hold a binary value of 9 or 1001.

one more thing use digit1==4'b1001 or 4'd9 as the condition instead of 9 after you change the declarations for digits.

Yes addign to what DAIXIWEN said the current status of the code might increase the digit values in all 4 block wrt to the clk .

If you want to increase the digit value when timer ==16000000 then it should be something like this

if (timer==16000000)

digit1<=digit1+1'b1;

this is not exactly what you should write but to make you understand when you should increase the digit1 value.

for your digit2 block it should be something like this

always @ (posedge clk)

begin

if (rst==0)

begin

digit2<=0;

end

else if(c1==1'b1)

begin

digit2<=digit2+1'b1;

end

else

begin

digit2<=digit2;

end

assign c2=(c1 && (digit2==4'd9));

and if its the same code you are implementing you have to write begin -end for the always block too.

like always @(..)

begin

if(..)

begin

..

end

else

begin

..

end

end //for always block begin

and yes the specs are not clear to me its a rough code i have written which are subjected to changes so be clear with what you are doing