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Altera_Forum
Honored Contributor
Honored ContributorDigital clock using verilog HDL
Hi, I need to design a clock using 7 segment with stop watch and alarm in Verilog HDL language. As I am new in these HDL I can not find any solution. Can anyone help me to do that? Eraesh
Altera_ForumHonored Contributor
Honored ContributorYou should handle each digit separately. Have the first digit count from 0 to 9. When you need to go over 9, put it back to 0 and increase the second digit. When that second digit is at 5 and you need to increase it again, put it back to 0 and increase the third digit, etc.
