Digital clock using verilog HDL

I'm not a verilog specialist, but for starters, I think there is a problem with your first digit.

If I understand correctly, you want to increase the digit by one each time your timer value resets (i.e. every 16000000 clock cycles). But you only do this test when the digit is 9. Furthermore you never put back the c1 signal at '0' so your other digits will increase on each clock cycle after that. You should do it this way:

[list][*]first test if reset is enabled, and in that case put the digit at 0

[*]else test if the timer is equal to your maximum value (or any fixed value in fact, you could use 0) and only then, do the following:[list][*]if the digit is 9, put it at 0 and assert the c1 signal[*]in the other cases, increase it by 1 and de-assert the c1 signal[/list][*]if the timer isn't equal to your fixed value, de-assert the c1 signal[/list]