Digital clock using verilog HDL

i have here the codes. but when i program the fpga, it displays 8888 only. it doesn't count. it was stationary.

module clock (clk, rst, m1, m2, m3, m4, a, b, c, d, e, f, g, dp);

input clk, rst;

output m1, m2, m3, m4;

output a, b, c, d, e, f, g, dp;

reg[23:0] timer;

reg[19:0] state;

reg[7:0] number, disp1, disp2, disp3, disp4;

reg c1, c2, c3, c4, digit1, digit2, digit3, digit4;

assign m1=digit1;

assign m2=digit2;

assign m3=digit3;

assign m4=digit4;

assign{a, b, c, d, e, f, g}=number;

assign dp=1;

parameter number1=7'b1001111;

parameter number2=7'b0010010;

parameter number3=7'b0000110;

parameter number4=7'b1001100;

parameter number5=7'b0100100;

parameter number6=7'b0100000;

parameter number7=7'b0001111;

parameter number8=7'b0000000;

parameter number9=7'b0000100;

parameter number0=7'b0000001;

always @(posedge clk)

if (rst==0)

state<=4'b0000;

else

state<=4'b1111;

always @ (posedge clk)

if (rst==0)

timer <=0;

else if (timer ==16000000)

timer <=0;

else

timer <= timer+1;

always @ (posedge clk)

if (rst==0)

begin

digit1<=0;

c1<=0;

end

else if (digit1==9&&timer==16000000)

begin

digit1<=0;

c1<=1;

end

else

begin

digit1<=digit1+1;

end

always @ (posedge clk)

if (rst==0)

begin

digit2<=0;

c2<=0;

end

else if (digit2==9&&c1)

begin

digit2<=0;

c2<=1;

end

else

begin

digit2<=digit2+1;

end

always @ (posedge clk)

if (rst==0)

begin

digit3<=0;

c3<=0;

end

else if (digit3==9&&c2)

begin

digit3<=0;

c3<=1;

end

else

begin

digit3<=digit3+1;

end

always @ (posedge clk)

if (rst==0)

begin

digit4<=0;

c4<=0;

end

else

begin

digit4<=digit4+1;

end

always @(posedge clk)

case (digit1)

4'b0000:disp1<=number0;

4'b0001:disp1<=number1;

4'b0010:disp1<=number2;

4'b0011:disp1<=number3;

4'b0100:disp1<=number4;

4'b0101:disp1<=number5;

4'b0110:disp1<=number6;

4'b0111:disp1<=number7;

4'b1000:disp1<=number8;

4'b1001:disp1<=number9;

default:disp1<= number0;

endcase

always @(posedge clk)

case (digit2)

4'b0000:disp2<=number0;

4'b0001:disp2<=number1;

4'b0010:disp2<=number2;

4'b0011:disp2<=number3;

4'b0100:disp2<=number4;

4'b0101:disp2<=number5;

4'b0110:disp2<=number6;

4'b0111:disp2<=number7;

4'b1000:disp2<=number8;

4'b1001:disp2<=number9;

default:disp2<= number0;

endcase

always @(posedge clk)

case (digit3)

4'b0000:disp3<=number0;

4'b0001:disp3<=number1;

4'b0010:disp3<=number2;

4'b0011:disp3<=number3;

4'b0100:disp3<=number4;

4'b0101:disp3<=number5;

4'b0110:disp3<=number6;

4'b0111:disp3<=number7;

4'b1000:disp3<=number8;

4'b1001:disp3<=number9;

default:disp3<= number0;

endcase

always @(posedge clk)

case (digit4)

4'b0000:disp4<=number0;

4'b0001:disp4<=number1;

4'b0010:disp4<=number2;

4'b0011:disp4<=number3;

4'b0100:disp4<=number4;

4'b0101:disp4<=number5;

4'b0110:disp4<=number6;

4'b0111:disp4<=number7;

4'b1000:disp4<=number8;

4'b1001:disp4<=number9;

default:disp4<= number0;

endcase

endmodule

**my problem is the increasing of the value of the second digit, and the third and the fourth. what is wrong with my codes.? do i need to use an identifier or any other special codes.? because the ones i used were the only thing i knew. as i have said, i only know basic stuffs. i know i should learn more. please help me. thanks. :)