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Dany2's avatar
Dany2
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9 months ago

differential clock input for EMIF agilex 5

Hi I'm working on the board of the agilex 5 with lpddr4. I want to input a clock from the external clock generator to the HSIO bank which is connected to the memory chip. The problem is that I do...
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sstrell's avatar
sstrell
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9 months ago

The EMIF is usually driven by a PLL clock. How are you clocking the rest of your design?

  • Dany2's avatar
    Dany2
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    9 months ago

    Yes, but I still can use an external clock and connect it to the IP. At least that's what is dome on the evaluation board