Forum Discussion

Dany2's avatar
Dany2
Icon for New Contributor rankNew Contributor
1 year ago

differential clock input for EMIF agilex 5

Hi I'm working on the board of the agilex 5 with lpddr4. I want to input a clock from the external clock generator to the HSIO bank which is connected to the memory chip. The problem is that I do...
Board Debug
Generic Io
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
1 year ago

The EMIF is usually driven by a PLL clock. How are you clocking the rest of your design?

  • Dany2's avatar
    Dany2
    Icon for New Contributor rankNew Contributor
    1 year ago

    Yes, but I still can use an external clock and connect it to the IP. At least that's what is dome on the evaluation board