Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

different width dual port ram from VHDL template

Dear all,

In my design I have a dual port memory, where the write port is 128x32 configuration and read port is 4096 x 1. I have written the module in the VHDL, but my implementation results in instauration of dual port memory with both ports having 32bits and lots of glue logic around.

When instantiating via megawizard, iget both ports cpnfigured correctly. That brings me a question:

1. What is the proper VHDL template to instantiate different bus width memory

2. How can i te-l to compiler, that this particular entity must be different bus width

3. Is there a way how to tell to compiler to instantiate such memory into m4k memory

4. Itseems that such memory configuration can be write-through instead of pipelines. How that changes the VHDL template?

As for 4. I'm asking because i have some fancy feeling, that when simulating the design, the simulator sometimes simulates the memory as write-through, whereas another times as pipelined.

The relevant piece of code is here. It contains as well some logic calculating number of bits set to 1 in all the memory. This is however irrelevant to issues asked here

http://svnweb.cern.ch/world/wsvn/fimdab/trunk/vhdl/fpga/sources/bunch_selection_memory/bunch_selection_memory.vhd

Thanks for any comment

David

12 Replies

Show More
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Well, this is of course the approach. But instantiating using megawizard renders the design not generic so when porting to xilinx this will require some additional work c whereas when written in pure VHDL, this step can be omitted. Unfortunately in my case the chance to swap the design to xilinx is slightly probable. In addition, Iprefer to write pure VHDL rather than using device specific stuff.

    Currently this design is built for stratix, this one has trimatrix. these are reasons for finding a way how to write generic VHDL. If I'd be able to specify in quartus setting file that particular entity is the m4k cell, that would be great.

    I've tried to use VHDL piece of code written in coding handbook to instantiate different bus width memory.this seems to work. still, it can be instantiated into m4k or higher. For the moment I'm letting quartus to decide what memory block it should use. Seems that its decision for the moment conforms with mine.

    D.

    --- Quote Start ---

    You did not mention the device or memory type in your post. I would recommend using Modelsim to simulate the memory.

    I have not seen Tcl commands for controlling the RAM inference. Rather, I use the MegaWizard to generate a template, and then copy and edit its internal instantiation of the altsyncram component.

    Cheers,

    Dave

    --- Quote End ---

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    Well, this is of course the approach. But instantiating using megawizard renders the design not generic so when porting to xilinx this will require some additional work c whereas when written in pure VHDL, this step can be omitted. Unfortunately in my case the chance to swap the design to xilinx is slightly probable. In addition, Iprefer to write pure VHDL rather than using device specific stuff.

    --- Quote End ---

    I also prefer portable VHDL, however, we don't live in a perfect world :)

    You can write code that can be re-targeted to Xilinx devices, or other memory types within the Altera device family by creating your own RAM component (port definitions). You can then use a VHDL configuration to map that component to an actual RAM device.

    This allows you to keep most of your code general purpose.

    I wrote a set of examples called vhdl_configurations.zip available at this thread:

    http://www.alteraforum.com/forum/showthread.php?t=30414&highlight=vhdl_configurations.zip&page=2

    Cheers,

    Dave