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Well, this is of course the approach. But instantiating using megawizard renders the design not generic so when porting to xilinx this will require some additional work c whereas when written in pure VHDL, this step can be omitted. Unfortunately in my case the chance to swap the design to xilinx is slightly probable. In addition, Iprefer to write pure VHDL rather than using device specific stuff.
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I also prefer portable VHDL, however, we don't live in a perfect world :)
You can write code that can be re-targeted to Xilinx devices, or other memory types within the Altera device family by creating your own RAM component (port definitions). You can then use a VHDL configuration to map that component to an actual RAM device.
This allows you to keep most of your code general purpose.
I wrote a set of examples called vhdl_configurations.zip available at this thread:
http://www.alteraforum.com/forum/showthread.php?t=30414&highlight=vhdl_configurations.zip&page=2 Cheers,
Dave
Honored Contributor
