Honored Contributor
Honored ContributorWell, this is of course the approach. But instantiating using megawizard renders the design not generic so when porting to xilinx this will require some additional work c whereas when written in pure VHDL, this step can be omitted. Unfortunately in my case the chance to swap the design to xilinx is slightly probable. In addition, Iprefer to write pure VHDL rather than using device specific stuff.
Currently this design is built for stratix, this one has trimatrix. these are reasons for finding a way how to write generic VHDL. If I'd be able to specify in quartus setting file that particular entity is the m4k cell, that would be great. I've tried to use VHDL piece of code written in coding handbook to instantiate different bus width memory.this seems to work. still, it can be instantiated into m4k or higher. For the moment I'm letting quartus to decide what memory block it should use. Seems that its decision for the moment conforms with mine. D. --- Quote Start --- You did not mention the device or memory type in your post. I would recommend using Modelsim to simulate the memory. I have not seen Tcl commands for controlling the RAM inference. Rather, I use the MegaWizard to generate a template, and then copy and edit its internal instantiation of the altsyncram component. Cheers, Dave --- Quote End ---
