different style of coding to reduce logic resources??

Question

I need to optimize my design in area. After setting all the required constraints, I started modifying the source code. I made few changes and see some changes in the resource Utilization.

Can anyone please tell me how this has reduced the logic as i dont see much difference in the code other than coding style has change from 1 case to the other.

The code is in verilog.

case 1:

always @(negedge clk or negedge rst_n)

begin

if ( rst_n == 0 )

begin

intr_reg <= 0;

intr_core <= 0;

end

else

begin

intr_reg <= { intr_reg[0], intr };

intr_core <= ( ((intr_reg == 2'b01) || (intr_core == 1)) && (intr_ack == 0) );

end

endmodule

Case 2: resource utilization has reduced by using the ternary operator

wire [ 1: 0] intr_wire;

assign intr_wire = { intr_wire[0], intr };

assign intr_core1 =( ((intr_reg == 2'b01) || (intr_core == 1)) && (intr_ack == 0));

always @(negedge clk or negedge rst_n)

begin

if ( rst_n == 0 )

begin

intr_reg <= 0;

intr_core <= 0;

end

else

begin

intr_reg <= intr_wire;

intr_core <= intr_core1;

end

endmodule

can anyone how this type of coding has reduced resource utilization.

Thank You

altera_forum · Answer

I don't really see how this could lead to a lower resource utilization, but you can have a look at the RTL viewer for both synthesises and see if you can find any differences.

altera_forum · Answer

Case 2 has NOT the same behavior as case 1.

While the <= assignment inside always block is performed only at clock edges,

statement assign intr_wire = { intr_wire[0], intr } is a continuous assignment (I mean combinatorial, clock independent); then you actually get intr_wire = { intr, intr }

and a few resources are spared.

You should have written:

assign intr_wire = { intr_reg[0], intr }

altera_forum · Answer

Good catch Cris72! I missed that!

altera_forum · Answer

Thank You.

I still do not see the difference between the two coding styles. In the example below, which is a stripped down example from case 1 and case 2 with the variables renamed, what extra logic is needed for r2 that is not needed for r1, It is my understanding that all RHS operations are combinatorial.

wire a;

wire b;

wire c;

reg [1:0] r1;

reg [1:0] r2;

assign c = { a, b };

always @(negedge clk or negedge rst_n)

begin

if ( rst_n == 0 )

begin

r1 <= 0;

r2 <= 0;

end

else

begin

r1 <= c;

r2 <= { a, b };

end

altera_forum · Answer

The actual RHS value for the assignment is evaluated at the clock edge, no logic is generated for the asign statement as such, in so far I don't see a difference between both coding styles.

Which difference do you see in the logic cell count and gate level logic implementation? I'm missing a complete module definition for the code in the first post to check for the claimed differences.

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different style of coding to reduce logic resources??

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