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Altera_Forum
Honored Contributor
Honored Contributordifferent style of coding to reduce logic resources??
I need to optimize my design in area. After setting all the required constraints, I started modifying the source code. I made few changes and see some changes in the resource Utilization. Can any...
Altera_ForumHonored Contributor
Honored ContributorThe actual RHS value for the assignment is evaluated at the clock edge, no logic is generated for the asign statement as such, in so far I don't see a difference between both coding styles.
Which difference do you see in the logic cell count and gate level logic implementation? I'm missing a complete module definition for the code in the first post to check for the claimed differences.
