Differences between accesing to HPS SDRAM from FPGA vía F2H and F2H_SDRAM

Question

Hi,all.  I´d seen the SoCkit Linaro Linux Desktop´s Quartus Project   ----&gt;&gt; http://rocketboards.org/foswiki/view/projects/sockitlinarolinuxdesktop  This example outputs linux video to the FPGA fabric.  In the fabric there is a framereader who reads the linux framebuffer and clocks video out.  I observed in the .QSYS that the VIP_framereader reads HPS SDRAM through the f2h bridge instead of doing this through the f2h_sdram interface.In fact there is no f2h_sdram interface enabled in the hps component propierties.  http://oi66.tinypic.com/15odkqg.jpg  I was working with the f2h_sdram interface enabling the h2f_sdram handoff etc... but never with the f2h bridge.  This other qsys system from Macnica uses my usual approach to access sdram (f2h_sdram bridge)  http://es.tinypic.com/view.php?pic=123kqz6&amp;s=9#.vtmdduyxtpg  What are the differences between this two approaches??  Thanks.

altera_forum · Answer

The f2h bridge goes through the L3 interconnect but the f2h_sdram goes directly to the memory controller. The f2h bridge can reach all the HPS devices, not just memory.

altera_forum · Answer

Thank you. I reviewed some block diagrams and you're right.So the correct approach deppends on the system to be implemented... Its not?

altera_forum · Answer

Yes. Also keep in mind that the f2h_sdram bridge bypasses the CPU cache. Your software either bare metal or device driver must be aware of that. Also be aware that the CPU and FPGA addresses may not match for the same piece of memory. If that is the case, you will need to compensate for that.

altera_forum · Answer

Yes, but everytime i use f2h_sdram bridge i do the following tho things:  - Reduce linux memory usage in uboot  - From fpga i only acces to the memory not used by the OS  But can i still have problems if i create the linux  frame buffer out of the linux 's used memory?  Are you refering to cache coherency problems?  Thank for the info, im not able to memorize all the soc datasheet xD  I think that its easier and takes less headache to use the f2h_bridge instead of the f2h_sdram one because the response it&amp;#351; still fine

altera_forum · Answer

The issue with cache coherency isn't that the memory is or is not being used by the kernel. Uboot sets all of memory to be cached by default because it doesn't know how much memory the kernel will use. For performance reasons you want to keep it that way.  If your frame buffer is double or triple buffered, flush cache (in the frame buffer only) before switching buffers. If your frame buffer is single buffered, you will need to flush after every series of writes to the frame buffer. If you use the f2h_bridge the accesses go through the cache, but you will get less performance. If you are OK with that use it.  Be aware that with single buffering you still won't see updates on the screen until the cache is flushed either explicitly by software or via normal operation. I don't know if SoC uses write back or write through.

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