Differences between accesing to HPS SDRAM from FPGA vía F2H and F2H_SDRAM

The issue with cache coherency isn't that the memory is or is not being used by the kernel. Uboot sets all of memory to be cached by default because it doesn't know how much memory the kernel will use. For performance reasons you want to keep it that way. If your frame buffer is double or triple buffered, flush cache (in the frame buffer only) before switching buffers. If your frame buffer is single buffered, you will need to flush after every series of writes to the frame buffer. If you use the f2h_bridge the accesses go through the cache, but you will get less performance. If you are OK with that use it. Be aware that with single buffering you still won't see updates on the screen until the cache is flushed either explicitly by software or via normal operation. I don't know if SoC uses write back or write through.