Differences between accesing to HPS SDRAM from FPGA vía F2H and F2H_SDRAM

Cache speeds up memory access for the CPU. Uboot and the kernel assumes that is what you want so it turns on cache for all of memory. Both uboot and the kernel manage cache when they are running. When software writes to memory, the cache and memory now probably hold different values. Depending on how the cache and memory systems work it may be quite a while before the content of memory and cache become the same. A cache flush for an address range causes any cache lines in that address range to be written to memory. It's necessary to do this in your software, because with the f2h_sdram bridge, that is the only time the FPGA sees that change.