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Altera_Forum
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10 years ago

Differences between accesing to HPS SDRAM from FPGA vía F2H and F2H_SDRAM

Hi,all. I´d seen the SoCkit Linaro Linux Desktop´s Quartus Project ---->> http://rocketboards.org/foswiki/view/projects/sockitlinarolinuxdesktop This example outputs linux video to t...
Altera_Forum's avatar
Altera_Forum
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10 years ago

Its a 5CSEMA4U23C6N (DE0 nanoSoC board) , sorry but i don´t understand how uboot sets the memory to be cacheable, who manages the caché and why flush is needed ...