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Altera_Forum's avatar
Altera_Forum
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10 years ago

Differences between accesing to HPS SDRAM from FPGA vía F2H and F2H_SDRAM

Hi,all.

I´d seen the SoCkit Linaro Linux Desktop´s Quartus Project

---->> http://rocketboards.org/foswiki/view/projects/sockitlinarolinuxdesktop

This example outputs linux video to the FPGA fabric.

In the fabric there is a framereader who reads the linux framebuffer and clocks video out.

I observed in the .QSYS that the VIP_framereader reads HPS SDRAM through the f2h bridge instead of doing this through the f2h_sdram interface.In fact there is no f2h_sdram interface enabled in the hps component propierties.

http://oi66.tinypic.com/15odkqg.jpg

I was working with the f2h_sdram interface enabling the h2f_sdram handoff etc... but never with the f2h bridge.

This other qsys system from Macnica uses my usual approach to access sdram (f2h_sdram bridge)

http://es.tinypic.com/view.php?pic=123kqz6&s=9#.vtmdduyxtpg

What are the differences between this two approaches??

Thanks.

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    The f2h bridge goes through the L3 interconnect but the f2h_sdram goes directly to the memory controller. The f2h bridge can reach all the HPS devices, not just memory.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Thank you. I reviewed some block diagrams and you're right.So the correct approach deppends on the system to be implemented... Its not?

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Yes. Also keep in mind that the f2h_sdram bridge bypasses the CPU cache. Your software either bare metal or device driver must be aware of that. Also be aware that the CPU and FPGA addresses may not match for the same piece of memory. If that is the case, you will need to compensate for that.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Yes, but everytime i use f2h_sdram bridge i do the following tho things:

    - Reduce linux memory usage in uboot

    - From fpga i only acces to the memory not used by the OS

    But can i still have problems if i create the linux frame buffer out of the linux 's used memory?

    Are you refering to cache coherency problems?

    Thank for the info, im not able to memorize all the soc datasheet xD

    I think that its easier and takes less headache to use the f2h_bridge instead of the f2h_sdram one because the response itş still fine
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    The issue with cache coherency isn't that the memory is or is not being used by the kernel. Uboot sets all of memory to be cached by default because it doesn't know how much memory the kernel will use. For performance reasons you want to keep it that way. If your frame buffer is double or triple buffered, flush cache (in the frame buffer only) before switching buffers. If your frame buffer is single buffered, you will need to flush after every series of writes to the frame buffer. If you use the f2h_bridge the accesses go through the cache, but you will get less performance. If you are OK with that use it. Be aware that with single buffering you still won't see updates on the screen until the cache is flushed either explicitly by software or via normal operation. I don't know if SoC uses write back or write through.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Its a 5CSEMA4U23C6N (DE0 nanoSoC board) , sorry but i don´t understand how uboot sets the memory to be cacheable, who manages the caché and why flush is needed ...

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Cache speeds up memory access for the CPU. Uboot and the kernel assumes that is what you want so it turns on cache for all of memory. Both uboot and the kernel manage cache when they are running. When software writes to memory, the cache and memory now probably hold different values. Depending on how the cache and memory systems work it may be quite a while before the content of memory and cache become the same. A cache flush for an address range causes any cache lines in that address range to be written to memory. It's necessary to do this in your software, because with the f2h_sdram bridge, that is the only time the FPGA sees that change.

  • JGros12's avatar
    JGros12
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    6 years ago

    Hello everybody,

    I have the Terasic DE10 Nano in a Cyclon V-SoC with 1 GB of external RAM. I can access the working memory via HPS (C code). So I can write values to a specific address space. Now I have to read these addresses in the FPGA. I know I need to add the F2H_SDRAM bridge, but I do not know how to write the VHDL code and the rest of the material.

    I have already reserved some memory (512 MB for Linux) in u-boot.

    For example, I would like to turn on an LED if the value is 48 in a particular DDR3 address.

    I just want to read the DDR3 address space. That's all.

    Can someone help me or give me a code? ....

    Many thanks