Honored Contributorhi,everyone.
i just start to use fpga cycloneIII,and i have a question which may be easy to answer. Thank you. question :is it right that VCCIO just supply the power?for example,if i want to use a bank to interface with a 3.3v device,i could VCCIO=2.5 and make sure VREF==3.3?
Honored ContributorYou can omit VREF pins if you are not using any voltage referenced IO standard. In this case you can use VREF pins just like any other IO. VCCIO is the main supply lines, which must be tied to the supply voltage, which is the expected IO supply, e.g., Connect 3.3V to VCCIO for 3.3V IO (using a 3.3V device).
Honored ContributorBD SLS
Thank you. IF interface fpga with 2.5v device,VREF must be connected to 2.5V,and VCCIO could be connected to 3.3V, and in this case,IO ports in this bank is 2.5V standard. Is it right?Honored ContributorHonored ContributorHonored ContributorVREF pins can be shared as IOs with all Cyclone devices, they are dedicated pins with Stratix and Arria.
Honored ContributorBe careful when using the VREF pins as fast I/O on the Cyclones, the VREF pins have a higher capacitance than the regular I/O pins.
Honored Contributorhow to configure a VREF pin as IO in cyclone 3 ?
there are commands line to add to qsf file ?Honored ContributorSimply assign them as IO. No additional settings required.
Honored ContributorHi,
I've red somewhere that 1.25V should be asserted to the VREF pins (with Cyclones III) when using the LVDS standard. However, I do not find anything clear about that in the device familly handbook... So if I use LVDS signalings with a bank, I must apply 2.5V to VCCIO pins and what about the VREF pins? Yours faithfullyHonored ContributorThe VREF pins aren't used with LVDS. They are only used with some fast single-ended iI/O standards, such as SSTL.
You can use those pins as regular I/O.
