DFE and CTLE reconfiguration in Arria V GZ

Hello, FPGA-engineers.

I have a problem with implementation RX equalization in 10GBASE-KR PHY IP in Arria V GZ.
My project works correctly with Auto-Negotiation (reconfiguration PMA), Link-Training (reconfiguration PCS) and FEC options.

But when I enable options "Enable RX equalization" in 10GBASE-KR PHY settings and "Enable DFE block", "Enable AEQ block" in Transceiver Reconfiguration Controller settings -- nothing happens.
I.e., the 10GBASE-KR PHY does not initiate a DFE and CTLE reconfiguration process. Signals dfe_start_rc and ctle_start_rc are always zero.
I tested in modelsim and in hardware. Why is this happening?

Screenshots of settings 10GBASE-KR PHY:

Screenshots of settings Transceiver Reconfiguration Controller:

Screenshots of settings Reset Controller:

Apart from this I found an old project example and there was a similar problem -- signals dfe_start_rc and ctle_start_rc are always zero.

Part of wave in Modelsim:

I will be grateful for any help.