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PPerd2's avatar
PPerd2
Icon for New Contributor rankNew Contributor
5 years ago
Solved

DFE and CTLE reconfiguration in Arria V GZ

Hello, FPGA-engineers. I have a problem with implementation RX equalization in 10GBASE-KR PHY IP in Arria V GZ. My project works correctly with Auto-Negotiation (reconfiguration PMA), Link-Train...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

For instance, you can reer to user guide page 579,580 (table 17-15, 17-16) for the register access of controlling AEQ register.


Thanks.


Reagrds,

dlim