Honored ContributorI want to implement this function : A<= B/x"A", when I compile, the Quartus put a notice: "/" used but didn't declare.
When I try with "*" (multiply) or "+" (add), it is ok. I don't know this error, Please help me. Thank you very much.
Honored ContributorAnd I didn't see it at first, but as the process is using signals and not variables, the Remainder and Result signals can be considered as fixed during the process execution, and only updated once you get out of the process. So in fact I think that the loop is infinite in any case.
Honored ContributorHonored Contributorsomething like this...
-- A_in/B_in = R (& rem remainder) -- R, rem initialised to zero -- A = abs(A_in), B = abs(B_in)
clked process...
rem <= A - B * R;
if rem >= B then
R <= R + 1;
else
result_out <= R; -- also decide sign here
remainder_out <= rem;
done <= '1';
end if;
if B = 0 then
alarm <= '1';
end if;
clked process...
rem <= A - B * R;
if rem >= B then
R <= R + 1;
else
result_out <= R; -- also decide sign here
remainder_out <= rem;
done <= '1';
end if;
if B = 0 then
alarm <= '1';
end if;
I had finished my program. But I don't know how to make sign for the value less than 0. Can you help me?
This is my code
library IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
--USE IEEE.numeric_std.all;
USE IEEE.std_logic_unsigned.all;
Entity Devide is
Port (
A,B : In std_logic_vector(7 downto 0); --A/B
Quotients,Remainder_out : Out std_logic_vector(7 downto 0);
CLK : In std_logic);
end Devide;
Architecture structural of Devide is
Signal Remainder,Divider : std_logic_vector(7 downto 0);--:=dividend;
Signal Result : std_logic_vector(7 downto 0);
Signal CNT : std_logic_vector(3 downto 0);
Begin
Process(clk)
Begin
if clk='1' and clk'event then
cnt<=cnt+1;
if cnt="0000" then
if B="00000000" then
cnt<="0000";
else
Remainder<= ABS (signed(A)); --Remainder = ABS(A)
Divider<= ABS (signed(B)); -- Divider = ABS(B)
end if;
elsif cnt="0001" and Remainder >= Divider then
Result<=Result+1;
Remainder<=Remainder-Divider;
elsif cnt="0010" and Remainder >= Divider then
cnt<="0001";
elsif cnt="0011" then
Quotients<=result;
Remainder_out<=Remainder;
elsif cnt="0100" then
cnt<="0000";
result<="00000000";
end if;
end if;
end process;
end structural;
comment out std_logic_arith and std_logic_unsigned packages. Bring back numeric_std package.
Then make remainder and divider signals signed types. You cannot assign a "signed" type to a std_logic_vector.Honored Contributor
library IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
Entity Devide is
Port (
A,B : In Signed(7 downto 0); --A/B
Quotients,Remainder_out : Out Signed(7 downto 0);
CLK : In std_logic);
end Devide;
Architecture structural of Devide is
Signal Remainder,Divider : Signed(7 downto 0);
Signal Result : Signed(7 downto 0);
Signal CNT : unSigned(3 downto 0);
Begin
Process(clk)
Begin
if clk='1' and clk'event then
cnt<=cnt+"1";
if cnt="0000" then
if B="00000000" then
cnt<="0000";
else
Remainder<= A;--ABS (signed(A)); --Remainder = ABS(A)
Divider<= B;--ABS (signed(B)); -- Divider = ABS(B)
end if;
elsif cnt="0001" and Remainder >= Divider then
Result<=Result+1;
Remainder<=Remainder-Divider;
elsif cnt="0010" and Remainder >= Divider then
cnt<="0001";
elsif cnt="0011" then
Quotients<=result;
Remainder_out<=Remainder;
elsif cnt="0100" then
cnt<="0000";
result<="00000000";
end if;
end if;
end process;
end structural;what you want to do is take the absolute of A and B, but also store the signedness of them and follow these rules:
If A and B are the same (ie. both positive or both negative), then result is positive. If A and B are different, then the result is negative. At the moment, you only ever create a postive result because you only ever add 1. You need to stick the XOR of MSBs of A and B into a shift register and then negate the output when needed.Honored Contributor
