Devide in VHLD

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comment out std_logic_arith and std_logic_unsigned packages. Bring back numeric_std package.

Then make remainder and divider signals signed types. You cannot assign a "signed" type to a std_logic_vector.

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Thanks tricky

I have a big problem with this code. If A,B> 0, It's OK. But A or B < 0. the result not correct.

Could you help me?

library IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
Entity Devide is
Port (
           A,B         : In Signed(7 downto 0); --A/B
           Quotients,Remainder_out   : Out Signed(7 downto 0);
           CLK        : In std_logic);
end Devide;
Architecture structural of Devide is
Signal Remainder,Divider  : Signed(7 downto 0);
Signal Result                 : Signed(7 downto 0);
Signal CNT                    : unSigned(3 downto 0);
Begin
Process(clk)
Begin
if clk='1' and clk'event then 
 cnt<=cnt+"1"; 
  if cnt="0000" then    
        if B="00000000" then
              cnt<="0000";
         else
              Remainder<= A;--ABS (signed(A)); --Remainder = ABS(A)
              Divider<= B;--ABS (signed(B)); -- Divider = ABS(B)
         end if;
  elsif cnt="0001" and Remainder >=  Divider then  
       Result<=Result+1;
       Remainder<=Remainder-Divider;
  elsif cnt="0010" and Remainder >= Divider then
       cnt<="0001";
  elsif cnt="0011" then
      Quotients<=result;
      Remainder_out<=Remainder;
  elsif cnt="0100" then
       cnt<="0000";
       result<="00000000";
  end if;
end if;
end process;
end structural;