Devide in VHLD

I had finished my program. But I don't know how to make sign for the value less than 0. Can you help me?

library IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
--USE IEEE.numeric_std.all;
USE IEEE.std_logic_unsigned.all;
Entity Devide is
Port (
	A,B				 			: In std_logic_vector(7 downto 0); --A/B
	Quotients,Remainder_out			: Out std_logic_vector(7 downto 0);
	CLK							: In std_logic);
end Devide;
Architecture structural of Devide is
Signal Remainder,Divider 	: std_logic_vector(7 downto 0);--:=dividend;
Signal Result 			: std_logic_vector(7 downto 0);
Signal CNT				: std_logic_vector(3 downto 0);
Begin
Process(clk)
Begin
if clk='1' and clk'event then 
	cnt<=cnt+1;	
	if cnt="0000" then 			
		if B="00000000" then
			cnt<="0000";
		else
			Remainder<= ABS (signed(A)); --Remainder = ABS(A)
			Divider<= ABS (signed(B)); -- Divider = ABS(B)
		end if;
	elsif cnt="0001" and Remainder >=  Divider then		
		Result<=Result+1;
		Remainder<=Remainder-Divider;
	elsif cnt="0010" and Remainder >= Divider then
		cnt<="0001";
	elsif cnt="0011" then
		Quotients<=result;
		Remainder_out<=Remainder;
	elsif cnt="0100" then
		cnt<="0000";
		result<="00000000";
	end if;
end if;
end process;
end structural;