Forum Discussion
New ContributorDesign works in ASE not on FPGA
Our design works in the ASE simulation environment. But it doesn't work on FPGA. Timing constraints are being met.
Please let us know as to what we might be missing / going wrong.
Thanks
Hi,
Thanks for the response. The steps to run on FPGA seems to require using AFU, which unfortunately I don't have the resources to.
Is it possible to share a tar.gz file of the Quartus project?
Also, in a previous comment you mentioned you want to view waveform generated in real time on FPGA, you can use Signal Tap Logic Analyzer: https://www.intel.com/content/www/us/en/docs/programmable/683819/21-3/logic-analyzer-introduction.html
If you want to do RTL simulation you can do so as well, here's an example: https://www.intel.com/content/www/us/en/docs/programmable/683870/22-1/quick-start-example-modelsim-with-verilog.html
Regards,
Nurina
17 Replies
NurinaRegular Contributor
Hi,
Thanks for the response. The steps to run on FPGA seems to require using AFU, which unfortunately I don't have the resources to.
Is it possible to share a tar.gz file of the Quartus project?
Also, in a previous comment you mentioned you want to view waveform generated in real time on FPGA, you can use Signal Tap Logic Analyzer: https://www.intel.com/content/www/us/en/docs/programmable/683819/21-3/logic-analyzer-introduction.html
If you want to do RTL simulation you can do so as well, here's an example: https://www.intel.com/content/www/us/en/docs/programmable/683870/22-1/quick-start-example-modelsim-with-verilog.html
Regards,
Nurina
sstrellSuper Contributor
Definitely need more info here. What is the design? What device are you targeting? What is not working? Can you provide some code? The people in this forum are good but we aren't mind readers!
Farabi_AlteraHello,
Please give us more information, otherwise I can't assign this case to the correct person.
regards,
Farabi
NavaneethHi,
Sure thanks. We're targetting Stratix 10 family. And the design is a 16x16 Matrix multiplier. The issue is - when we configure the FPGA with the GBS file ( that has met timing constraints ) and then run the software, we get all zeroes as output but on ASE, it gives the correct output. We're using the streaming dma afu as the basic building block. And we've included our design in the avst_decimator.sv file ( which was doing a loopback ).
Can you please by mentioning a list of possible things we can do to debug this issue?
Also, can you please let us know if there's a way to view waveform generated in real time on FPGA?
- AGORS5
JohnT_AlteraHi,
Can you share with us the code and step to duplicate the issue so that we can further look into the issue?
- Nurina
Hello,
Could you share the .qar file? To do this, go to Project->Archive Project
Regards,
Nurina
- Navaneeth
- Nurina
Hi,
Are you using Quartus Prime Pro v19.2?
Regards,
Nurina
- Navaneeth
Hi,
We are using the following version of Quartus:
Info: Running Quartus Prime Shell
Info: Version 18.1.2 Build 277 02/12/2019 Patches 2.02,2.03,2.06 SJ Pro EditionApologies for the misleading name
Regards,
Navaneeth M - Nurina
Hi Navaneeth,
Thank you for the response. I received below error, is there anything I should re-generate/import?
Error(16045): Instance "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|shim|ccip_std_afu" instantiates undefined entity "ccip_std_afu"
Error(16185): Can't elaborate user hierarchy "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|shim|ccip_std_afu"
Error(16185): Can't elaborate user hierarchy "fpga_top|inst_green_bs|platform_shim_ccip_std_afu|shim"
Error(16185): Can't elaborate user hierarchy "fpga_top|inst_green_bs|platform_shim_ccip_std_afu"
Regards,
Nurina
