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Navaneeth's avatar
Navaneeth
Icon for New Contributor rankNew Contributor
3 years ago
Solved

Design works in ASE not on FPGA

Hi, Our design works in the ASE simulation environment. But it doesn't work on FPGA. Timing constraints are being met. Please let us know as to what we might be missing / going wrong. Thanks
Farabi's avatar
Farabi
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hello,


Please give us more information, otherwise I can't assign this case to the correct person.


regards,

Farabi


  • Navaneeth's avatar
    Navaneeth
    Icon for New Contributor rankNew Contributor
    3 years ago
    Hi,
    Sure thanks. We're targetting Stratix 10 family. And the design is a 16x16 Matrix multiplier. The issue is - when we configure the FPGA with the GBS file ( that has met timing constraints ) and then run the software, we get all zeroes as output but on ASE, it gives the correct output. We're using the streaming dma afu as the basic building block. And we've included our design in the avst_decimator.sv file ( which was doing a loopback ).

    Can you please by mentioning a list of possible things we can do to debug this issue?
    Also, can you please let us know if there's a way to view waveform generated in real time on FPGA?