Forum Discussion
New ContributorDesign works in ASE not on FPGA
Hi,
Thanks for the response. The steps to run on FPGA seems to require using AFU, which unfortunately I don't have the resources to.
Is it possible to share a tar.gz file of the Quartus project?
Also, in a previous comment you mentioned you want to view waveform generated in real time on FPGA, you can use Signal Tap Logic Analyzer: https://www.intel.com/content/www/us/en/docs/programmable/683819/21-3/logic-analyzer-introduction.html
If you want to do RTL simulation you can do so as well, here's an example: https://www.intel.com/content/www/us/en/docs/programmable/683870/22-1/quick-start-example-modelsim-with-verilog.html
Regards,
Nurina
Regular ContributorHello,
Please give us more information, otherwise I can't assign this case to the correct person.
regards,
Farabi
NavaneethHi,
Sure thanks. We're targetting Stratix 10 family. And the design is a 16x16 Matrix multiplier. The issue is - when we configure the FPGA with the GBS file ( that has met timing constraints ) and then run the software, we get all zeroes as output but on ASE, it gives the correct output. We're using the streaming dma afu as the basic building block. And we've included our design in the avst_decimator.sv file ( which was doing a loopback ).
Can you please by mentioning a list of possible things we can do to debug this issue?
Also, can you please let us know if there's a way to view waveform generated in real time on FPGA?
