Design works in ASE not on FPGA

Hi,

Thanks for the response. The steps to run on FPGA seems to require using AFU, which unfortunately I don't have the resources to.

Is it possible to share a tar.gz file of the Quartus project?

Also, in a previous comment you mentioned you want to view waveform generated in real time on FPGA, you can use Signal Tap Logic Analyzer: https://www.intel.com/content/www/us/en/docs/programmable/683819/21-3/logic-analyzer-introduction.html

If you want to do RTL simulation you can do so as well, here's an example: https://www.intel.com/content/www/us/en/docs/programmable/683870/22-1/quick-start-example-modelsim-with-verilog.html

https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/quartus/simulation-nativelink-howto.html?wapkw=quartus%20simulation

Regards,

Nurina