Design works in ASE not on FPGA

Hi,

We haven't received any such errors. The ccip_std_afu is located in the hw/rtl/ccip_std_afu.sv file.

We're using the streaming-dma-afu BBB as our base design and we've included our files - split.sv and cmm_top.sv ( our matrix multiplier verilog code file ) - in hw/rtl/QSYS_IPS/avst_decimator folder.

Hi,

I've included the modules in hw/rtl/ but I still see some errors related to it.

Error(13406): Verilog HDL error at afu.sv(31): object "ccip_avmm_pkg" is not declared

Error(13406): Verilog HDL error at afu.sv(139): object "CCIP_AVMM_REQUESTOR_DATA_WIDTH" is not declared

Error(17457): Verilog HDL error at afu.sv(139): range must be bounded by constant expressions

Error(14395): Verilog HDL error at afu.sv(140): CCIP_AVMM_REQUESTOR_WR_ADDR_WIDTH is not a constant

Error(17457): Verilog HDL error at afu.sv(140): range must be bounded by constant expressions

Error(13406): Verilog HDL error at afu.sv(142): object "CCIP_AVMM_REQUESTOR_BURST_WIDTH" is not declared

Error(17457): Verilog HDL error at afu.sv(142): range must be bounded by constant expressions

Error(13406): Verilog HDL error at afu.sv(147): object "CCIP_AVMM_REQUESTOR_DATA_WIDTH" is not declared

Error(17457): Verilog HDL error at afu.sv(147): range must be bounded by constant expressions

Error(13406): Verilog HDL error at afu.sv(149): object "CCIP_AVMM_REQUESTOR_DATA_WIDTH" is not declared

Error(17457): Verilog HDL error at afu.sv(149): range must be bounded by constant expressions

Error(13406): Verilog HDL error at afu.sv(150): object "CCIP_AVMM_REQUESTOR_RD_ADDR_WIDTH" is not declared

Error(17457): Verilog HDL error at afu.sv(150): range must be bounded by constant expressions

Error(13406): Verilog HDL error at afu.sv(153): object "CCIP_AVMM_REQUESTOR_BURST_WIDTH" is not declared

Error(17457): Verilog HDL error at afu.sv(153): range must be bounded by constant expressions

Error(13406): Verilog HDL error at afu.sv(156): object "CCIP_AVMM_MMIO_DATA_WIDTH" is not declared

Error(17457): Verilog HDL error at afu.sv(156): range must be bounded by constant expressions

Error(13406): Verilog HDL error at afu.sv(158): object "CCIP_AVMM_MMIO_DATA_WIDTH" is not declared

Error(17457): Verilog HDL error at afu.sv(158): range must be bounded by constant expressions

Error(16827): Verilog HDL error at ccip_std_afu.sv(34): cannot open include file cci_mpf_if.vh

Error(13406): Verilog HDL error at ccip_std_afu.sv(35): object "cci_mpf_csrs_pkg" is not declared

Received this critical warning:

Critical Warning(125091): Tcl error: couldn't read file "../../hw/rtl/BBB_ccip_avmm/hw/par/ccip_avmm_addenda.qsf": no such file or directory while executing "source ../../hw/rtl/BBB_ccip_avmm/hw/par/ccip_avmm_addenda.qsf" (file "../hw/afu.qsf" line 6)

The project I received doesn't have the folder ../../hw/rtl/BBB_ccip_avmm/hw/par/

Is this required in the project?

Regards,

Nurina

Hi,

Sorry for the delayed response.

Can you please try with https://drive.google.com/file/d/1K9rg_u6i57mGkBegACfYQz5UjMJiNV8N/view?usp=share_link?

Steps to run ASE ( after extracting the tar.gz file

1. cd Capstone-Streaming-DMA-AFU

2. afu_sim_setup --source=./hw/rtl/filelist.txt build_ase_dir

3. cd build_ase_dir

4. make -j16 ( takes around 5 minutes )

5. two screen sessions are needed

On first:

1. make sim -j16

2. < copy the export path >

On second:

1. cd sw

2. < paste the export path >

3. make USE_ASE=1

4. ./fpga_dma_st_test -l on -s 2048 -p 64 -t fixed -f 0

Steps to run on FPGA:

1. cd Capstone-Streaming-DMA-AFU

2. afu_synth_setup --source=./hw/rtl/filelist.txt build_synth_dir

3. cp afu_default.qsf build_synth_dir/build/

4. cp flame-job-script.sh build_synth_dir

5. cd build_synth_dir

6. ./flame-job-script.sh ( takes around 2 hours )

7. fpgaconf streaming_dma_afu.gbs

8. cd ../sw

9. make

10. ./fpga_dma_st_test -l on -s 2048 -p 64 -t fixed -f 0

Thanks,
Navaneeth M

Hi,

May I know if you have any updates?

Regards,

Nurina

Hi,

We do not receive any response from you on the previous reply provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 4/5 survey

Regards,

Nurina