Forum Discussion
New ContributorDesign works in ASE not on FPGA
Hi,
Thanks for the response. The steps to run on FPGA seems to require using AFU, which unfortunately I don't have the resources to.
Is it possible to share a tar.gz file of the Quartus project?
Also, in a previous comment you mentioned you want to view waveform generated in real time on FPGA, you can use Signal Tap Logic Analyzer: https://www.intel.com/content/www/us/en/docs/programmable/683819/21-3/logic-analyzer-introduction.html
If you want to do RTL simulation you can do so as well, here's an example: https://www.intel.com/content/www/us/en/docs/programmable/683870/22-1/quick-start-example-modelsim-with-verilog.html
Regards,
Nurina
New ContributorHi,
Sorry for the delayed response.
Can you please try with https://drive.google.com/file/d/1K9rg_u6i57mGkBegACfYQz5UjMJiNV8N/view?usp=share_link?
Steps to run ASE ( after extracting the tar.gz file
1. cd Capstone-Streaming-DMA-AFU
2. afu_sim_setup --source=./hw/rtl/filelist.txt build_ase_dir
3. cd build_ase_dir
4. make -j16 ( takes around 5 minutes )
5. two screen sessions are needed
On first:
1. make sim -j16
2. < copy the export path >
On second:
1. cd sw
2. < paste the export path >
3. make USE_ASE=1
4. ./fpga_dma_st_test -l on -s 2048 -p 64 -t fixed -f 0
Steps to run on FPGA:
1. cd Capstone-Streaming-DMA-AFU
2. afu_synth_setup --source=./hw/rtl/filelist.txt build_synth_dir
3. cp afu_default.qsf build_synth_dir/build/
4. cp flame-job-script.sh build_synth_dir
5. cd build_synth_dir
6. ./flame-job-script.sh ( takes around 2 hours )
7. fpgaconf streaming_dma_afu.gbs
8. cd ../sw
9. make
10. ./fpga_dma_st_test -l on -s 2048 -p 64 -t fixed -f 0
Thanks,
Navaneeth M
