Honored ContributorI am new to the CPLD design. Can I use a buffer to delay my clock just for one cycle then in Quartus II's megafuction? Or is there a clock delay megafuntion in Quartus II library?
Honored ContributorWhat are you trying to do? Delaying a clock by one cycle does nothing, eg. a square wave delayed by one period is exactly the same square wave.
Please explain more clearly what you want to do. If you want to delay a signal by one clock period, then you can use a register. Cheers, DaveHonored ContributorI have a signal coming in from the external source that is trigger base on the input clock’s positive edge. I would like to shift the input clock cycle’s one cycle so that I can delay one clock cycle later to match my process time in the CPLD.
Honored ContributorThe image you have drawn is incorrect. If you have a signal that is a pulse relative to a clock, then it will last for a full clock period, not half a period as you have shown.
Given an external signal 'd', you can delay it one clock to give an output 'q' using a register, eg. in VHDL process(clk) begin if rising_edge(clk) then q <= d; end if; end process; If 'd' is pulsed, then 'q' will pulse one clock later. In either case, the clk signal is not delayed, it is the signal that is delayed by one clock. Cheers, DaveHonored ContributorIn your image, you have drawn the input pulse for only half a clock period, and you have drawn your second clock shifted by half a clock period.
If you describe what you are trying to do in a more general sense, I can probably help you understand things a little better. For example, where is this pulse coming from, and what ensures that it is synchronous to the external clock signal? Does the pulse last for more than a clock period, or is it really half a period as you have shown? Cheers, DaveHonored ContributorThe inputs are coming from a chip’s output. Yes, indeed it is half of clock cycle. I have a reference clock in my system and the trigger stage that looks like the shifted input’s signal position. The input clock that comes out from this chip is changing once a while. Sometime it is leading the reference clock half the cycle. If it did leading the reference clock then the input signal will not line up with my system’s trigger signal. I would like to compare the input signal to my system’s reference signal. I set my system’s clock to have the same frequency at the input clock. For example, if I could not detect the input signal is lining up with my system’s reference’s signal the I have to shift the input clock half a cycle to match it. Thanks Dave.
Honored ContributorOk, so you really have two clock domains here; one for the chip generating the pulse, and another for your FPGA.
You have a couple of options; 1) Using the same frequency clock in the FPGA you can generate a toggle signal, eg., lets say 'pulse' is your input, then you can generate a toggle signal by using the pulse as a clock, eg. in VHDL signal toggle : std_logic := '0'; process(pulse) begin if rising_edge(pulse) then toggle <= not toggle; end if; then you would synchronize this togglng signal to the FPGA clock, and delay the synchronized signal one clock more. The xor of the synchronized signal and the delayed by one clock signal will be a one-clock high pulse in the FPGA clock domain. 2) Use an FPGA clock with a period that is shorter than the pulse width. In this case, the pulse will last multiple FPGA clocks, so you do not need the toggle logic, just a synchronizer, a delay, and the xor gate to create the pulse in the local clock domain. Does this make sense? Cheers, DaveHonored ContributorYes, I do have two clocks. Let me try out these two different methods.
Thanks Dave
