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Altera_Forum's avatar
Altera_Forum
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14 years ago

Delaying 1 cycle in my clock

I am new to the CPLD design. Can I use a buffer to delay my clock just for one cycle then in Quartus II's megafuction? Or is there a clock delay megafuntion in Quartus II library?
Altera_Forum's avatar
Altera_Forum
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14 years ago

Ok, so you really have two clock domains here; one for the chip generating the pulse, and another for your FPGA.

You have a couple of options;

1) Using the same frequency clock in the FPGA you can generate a toggle signal, eg., lets say 'pulse' is your input, then you can generate a toggle signal by using the pulse as a clock, eg. in VHDL

signal toggle : std_logic := '0';

process(pulse)

begin

if rising_edge(pulse) then

toggle <= not toggle;

end if;

then you would synchronize this togglng signal to the FPGA clock, and delay the synchronized signal one clock more. The xor of the synchronized signal and the delayed by one clock signal will be a one-clock high pulse in the FPGA clock domain.

2) Use an FPGA clock with a period that is shorter than the pulse width. In this case, the pulse will last multiple FPGA clocks, so you do not need the toggle logic, just a synchronizer, a delay, and the xor gate to create the pulse in the local clock domain.

Does this make sense?

Cheers,

Dave