Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorDelaying 1 cycle in my clock
I am new to the CPLD design. Can I use a buffer to delay my clock just for one cycle then in Quartus II's megafuction? Or is there a clock delay megafuntion in Quartus II library?
Altera_ForumHonored Contributor
Honored ContributorThe inputs are coming from a chip’s output. Yes, indeed it is half of clock cycle. I have a reference clock in my system and the trigger stage that looks like the shifted input’s signal position. The input clock that comes out from this chip is changing once a while. Sometime it is leading the reference clock half the cycle. If it did leading the reference clock then the input signal will not line up with my system’s trigger signal. I would like to compare the input signal to my system’s reference signal. I set my system’s clock to have the same frequency at the input clock. For example, if I could not detect the input signal is lining up with my system’s reference’s signal the I have to shift the input clock half a cycle to match it. Thanks Dave.
