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Altera_Forum
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14 years ago

Delaying 1 cycle in my clock

I am new to the CPLD design. Can I use a buffer to delay my clock just for one cycle then in Quartus II's megafuction? Or is there a clock delay megafuntion in Quartus II library?
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I have a signal coming in from the external source that is trigger base on the input clock’s positive edge. I would like to shift the input clock cycle’s one cycle so that I can delay one clock cycle later to match my process time in the CPLD.