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Altera_Forum's avatar
Altera_Forum
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14 years ago

Delaying 1 cycle in my clock

I am new to the CPLD design. Can I use a buffer to delay my clock just for one cycle then in Quartus II's megafuction? Or is there a clock delay megafuntion in Quartus II library?
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

The image you have drawn is incorrect. If you have a signal that is a pulse relative to a clock, then it will last for a full clock period, not half a period as you have shown.

Given an external signal 'd', you can delay it one clock to give an output 'q' using a register, eg. in VHDL

process(clk)

begin

if rising_edge(clk) then

q <= d;

end if;

end process;

If 'd' is pulsed, then 'q' will pulse one clock later.

In either case, the clk signal is not delayed, it is the signal that is delayed by one clock.

Cheers,

Dave