Delay in SPI-to-Avalon-MM IP Response After MAX10 Reset

Hi chrissynco,

Sorry for the delay in responding to the thread, didn't notice about the reply posting failure due to login timeout, had to retype my reply.

As for your question I did a search around our database, what I could say is there is a no hard defined startup time for the FPGA and IP to begin responding, it could be a combination of different factors.

From the behavior that you observed :

CONF_DONE goes high

PLL lock asserts (system leaves reset?)

9ms respond from SPI core to SPI traffic

CONF_DONE goes high indicates FPGA configuration received and then finishes initialization then only enter user mode. From the documentation I saw from Agilex/Stratix 10, recommendation is to hold logic in reset until all fabric is in user mode.

Note: The entire device does not enter user mode simultaneously. Intel recommends that you follow the Including the Reset Release Intel FPGA IP in Your Design to hold your application logic in the reset state until the entire FPGA fabric is in user mode.

https://www.intel.com/content/www/us/en/docs/programmable/683762/22-1/conf-done-and-init-done.html

https://www.intel.com/content/www/us/en/docs/programmable/683539/20-4/using-the-reset-release.html

For MAX10 there is no INIT_DONE but it have internal tCD2UM with min-max wait time (in uS). https://www.intel.com/content/www/us/en/docs/programmable/683794/current/internal-configuration-timing-parameter.html

Maybe do look into the reset release mechanism is it after FPGA enters user mode.

The other area to look at probably at the SPI Core The SPI core logic is synchronous to the clock input provided by the Avalon-MM interface. It will not able to response just by SCLK alone until the Avalon clock is running and reset de-asserted. See whether is there any gating item that introduces delay in this area.

https://www.intel.com/content/www/us/en/docs/programmable/683094/22-1/serial-port-interface-spi.html

How about the power rails that is controlled by the load switch from the microprocessor, does the voltage instantly stable or does it ramp up over few ms?

Some additional documentation

Max10 FPGA configuration user guide

https://www.intel.com/content/www/us/en/docs/programmable/683865/current/fpga-configuration-overview.html

Thanks

Regards

Kian