Altera_Forum
Honored Contributor
14 years agoDefault Value for Bidirectional differential signal
Hey everyone,
I am creating a parametrized project which synthesizes a DDR2 controller only when the user specifies it is needed via a generate statement. There are 2 differential clock pins which are SSTL-II Differential output standards. I would prefer not to change this standard when the pins are not being used, and wanted to assign the signal default to a TRISTATE when the DDR2 controller is not being generated. Unfortunately, when tristating the signal in question, I get an error from the fitter stating that a bidirectional differential signal MUST use an output enable. I can understand this is good check for most cases, but how is defaulting the signal to a tristate not a valid assignment? The output enable is being used, since it is always disabled. To fix this, I created an always disabled ALT_IO_BUF, but I am guessing the synthesizer is just translating it to a tristate assignment anyways, so the fitter throws the same error. Any ideas? Thank you.