Altera_ForumHonored Contributor14 years agoDefault Value for Bidirectional differential signal Hey everyone, I am creating a parametrized project which synthesizes a DDR2 controller only when the user specifies it is needed via a generate statement. There are 2 differential clock pins wh...Show More
Altera_ForumHonored Contributor14 years agoDon't you have tristate option of unused pins in the project settings?
Recent DiscussionsTrouble Getting started with Stratix 10 SOCSolvedJTAG Chain Broken on Agilex 7-I Dev KitAgilex 5 PowerIssue with configuring EPCQ64A & Cyclone10LP using NiosV as processor.Agilex5 A5EB013BB23BE4S BSDLSolved